In production processes of a semiconductor device, when patterning, photolithographic processing is frequently used. In a conventional patterning, the photolithographic processing is carried out on a semiconductor wafer using a transfer mask (reticle).
In fabrication of the transfer mask (reticle) used in the photolithographic processing, first a resist film is formed on a chromium film formed on a silica-based substrate. Next, the resist film is exposed by light or an electron beam based on design data, then developed to form a resist mask having a predetermined pattern. Then, the chromium film is etched using the resist mask as a etching mask to form pattern aperture and thereby fabricate the desired transfer mask.
However, with patterning processes by photolithographic processing using the transfer mask, it is becoming more difficult to handle the formation of fine patterns along with miniaturization of semiconductor devices.
That is, along with the improvement in the degree of the integration of LSIs, lithographic technology enabling finer processing has being demanded. To respond to this, next generation electron-beam lithographic technology such as LEEPL (Low Energy E-beam Proximity Projection Lithography) and EPL is being developed.
In next generation electron-beam lithographic technology, instead of a transfer mask comprised of the above-mentioned silica-based substrate, a stencil mask fabricated by directly forming pattern apertures in a membrane consisting of Si, diamond, or the like based on design data is being used.
However, with a stencil mask, since pattern apertures are directly formed in the membrane region to form the pattern, it is physically impossible to fabricate for example a doughnut-shaped (annular-shaped) pattern. Namely, it is not possible to support the membrane at the inside.
Therefore, “a complementary divided technology” using a complementary stencil mask dividing a single pattern into two or more blocks and performing overlay exposure on a semiconductor wafer is being developed. For example, when forming a doughnut-shaped pattern, two mask regions having pattern apertures dividing the doughnut-shaped pattern into halves are formed based on design data of the doughnut-shaped pattern. Then, the patterns of the mask regions are exposed overlapped to transfer the doughnut-shaped pattern on the semiconductor wafer.
Here, in the present description, a “stencil mask” is defined as a mask having aperture regions where substance does not exist in a space.
A “complementary divided mask” is defined as a mask dividing a pattern of a certain section and placing the parts on different mask region and able to form the pattern of that section as before division by making the mask regions overlap to make divided parts of the pattern overlap.
A “complementary divided stencil mask” is defined as a stencil mask dividing a pattern of a certain section and placing the parts on different mask region and able to form the pattern of that section as before division by making the mask region overlap to make divided parts of the pattern overlap.
In the lithographic technology using proximity exposure such as the above LEEPL, control of the gap between the mask and the semiconductor wafer is important.
In LEEPL, to control the gap, for example, the SLA alignment method developed by Sumitomo Heavy Industries Co., Ltd. and actually used in equal magnification X-ray lithography is employed.
The SLA alignment method is die-by-die alignment method which simultaneously detects marks and signals on complementary divided stencil masks for the respective drawing regions. Due to this, it measures and controls the relative positions of the semiconductor wafer and the complementary divided stencil masks and the gap between the semiconductor wafer and the complementary divided stencil masks.
The masks are aligned by die-by-die alignment method or global alignment method.
Die-by-die alignment method is a method measuring the positions of alignment marks formed at a previous step on a semiconductor wafer for the respective shots and using these to align the masks and determine the exposure position. This method can even handle expansion and contraction differing by location on the semiconductor wafer and promises a high alignment precision.
On the other hand, global alignment method is a method first measuring the positions of alignment marks of a plurality of points on a semiconductor wafer to determine the coordinates of the respective shots in the semiconductor wafer and moving and exposing the semiconductor wafer according to the coordinates. To use this method, a means for accurately measuring the coordinate position of the semiconductor wafer is necessary.
However, with die-by-die alignment method, as explained below, there was the problem of a difficulty of control of the relative positions of the complementary divided stencil masks and the semiconductor wafer. Control of the relative positions of the complementary divided stencil masks and a semiconductor wafer is called “alignment”.
For example, consider the case of exposure using equal magnification transfer type complementary four-divided stencil masks as shown in FIG. 1. As shown in FIG. 1, the equal magnification transfer type complementary four-divided stencil masks 10 divide a single pattern into four different patterns. First to fourth masks 10A to 10D the respective having one of the four different patterns are connected to form a single mask.
When using the complementary four-divided stencil mask 10 to expose a semiconductor wafer, it is possible to alternately use the first to fourth masks 10A to 10D to expose a single chip region to transfer a single pattern to the chip region.
The method of alignment of the complementary four-divided stencil masks by die-by-die alignment method will be described next. Generally, as shown in FIG. 2, alignment is performed using alignment marks 16 provided at the four corners of a set of four chips of a semiconductor wafer 12 corresponding to the size of the complementary divided mask, that is, the four chip region 14. Note that a “chip region” indicates a region corresponding to one semiconductor chip. Further, in the illustrated example, the four chips regions correspond to a scan area of an electron beam in a single exposure, that is, a single exposure region or exposure field.
At that time, as shown in FIG. 2, exposure regions including chip regions 18 (chip regions marked X in FIG. 2) at the outer circumference portion of the semiconductor wafer lack one or more of the necessary alignment marks, so alignment of the complementary divided stencil mask is not possible.
Further, although aligning by global alignment method is possible, since the average of the entire semiconductor wafer is taken to calculate the alignment coefficients, there was the problem that higher order distortion of the underlying semiconductor wafer could not be corrected.
In this way, due to the problem in the alignment of complementary divided stencil masks, it is difficult to use complementary divided stencil masks to accurately transfer a desired pattern to a semiconductor.